The need for very high speed large memory capacity computers is leading to the use of wafer scale integration which uses a single silicon wafer as the carrier for tens, or hundreds, or thousands of integrated circuits which are formed in the wafer and are separated from each other by p-n junction or dielectric isolation. Conductors formed on or over the top planar surface of the wafer serve to interconnect the circuits. Another similar approach is to attach wholly formed integrated circuits to a semiconductor wafer and then to interconnect the circuits with conductors. One such implementation is described in the article entitled "Wafer-Chip Assembly for Large-Scale Integration," IEEE Transactions on Electron Devices, Vol. ED-15, No. 9, September, 1968, pp. 660-663. Other implementations and methods of forming such implementations are described in the four patent applications which are cross-referenced above.
In most of these structures multiple integrated circuits are coupled to a common data bus with each also being coupled to common arbitration circuitry which determines which circuit gains access to the data bus if two or more circuits seek access at essentially the same time or within a preselected time period. One problem with the common arbitration circuitry is that it adds to the wiring complexity and therefore limits the number of circuits which can be used on or in a given semiconductor wafer and requires two interchip transactions which adversely affects speed performance.
It would be desirable to achieve the needed arbitration functions for multiple circuits having a common data bus without incurring the wiring and speed penalties of prior art structures.